It is known, in binary sequences or binary words of a specific length n, to correct arbitrary 1-bit errors, 2-bit errors and 3-bit errors in parallel using BCH codes by means of combinational error correction circuits. This is described for example in US 2015/0039976A1. It is disadvantageous here that not more than 3-bit errors can be corrected.
U.S. Pat. No. 8,291,303 B2 describes a method for correcting 4-bit errors. What is disadvantageous in that case is that solving a fourth-degree equation is reduced in a complicated manner to solving two second-degree equations; as a result, the decoding becomes slow and requires a high outlay on circuitry. Furthermore, it is disadvantageous that no t-bit errors where t>4 can be corrected.